AOR AR-ONE Specifications download pdf (Page 62)

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1X TMS320C6713 @ 225MHz

32 MB of SDRAM @ 100MHz

OTAG Port

VIRTEX-II FPGA

XC2V3000-FF1152

DSP's EMIF signals directly connected to the FPGA.

Dedicated 32 MB (8X32-bits) SDRAM

JTAG Port of FPGA is available on a 6-pins header

(Parallel Cable 3 compatible).

MCU

ELANSC520-100AC

2 X 2MB FLASH , 32MB SDRAM

LCD

Ethernet Controller

2 Serial Ports (1 DB-9 + 1 header)

ADC

Analog Devices' AD6644

65MHz Sampling Frequency

DC-Coupled

Analog Programmable Gain

Acquisition Clock : Programmable Clock or External Clock

Digital I/Os

3 external Virtex-II GPIOs

DAC

Analog Devices' AD9754

125 MHz Sampling Frequency maximum

DC-Coupled

Acquisition Clock : Programmable Clock or driven by FPGA

Video Decoder

Philips SAA7111A

Supports 8-bits and 16-bits data path

Video Encoder Analog Devices ADV7171

Supports 8-bits and 16-bits data path

Audio CODEC

Burr-Brown PCM3008

Audio Sampling Frequency from 8 kHz to 48 kHz

Sample resolution 16-bits

User Story: description of an HF SSB radio based on the SignalMaster DSP/FPGA architecture. Uses

Mathworks' Simulink system-level tool as the principal development environment.

TORNADO-PX/DDC4G rev.2x

Quad Channel Multi-Standard 105 MSPS Digital Radio Receiver Coprocessor/Controller for TORNADO DSP

Boards and Stand-alone Applications. Made in Russia

General features

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AOR AR-ONE Specifications Page 62

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